問題詳情
13. Consider a pipelined datapath to process instructions and is consisted of five steps: Fetch instruction, Decode instruction,Execute instruction, Memory access, Write Back and the processing times are 0.4 ns, 0.25 ns, 0.2 ns, 0.4 ns, and 0.33 ns,respectively. If we want to design a control circuit to operate the pipelined datapath, what is the clock rate?
(A) 2.5 GHz
(B) 4 GHz
(C) 5 GHz.
(D) 3 GHz
參考答案
答案：[無官方正解]
難度：計算中-1
書單：沒有書單，新增