問題詳情
2. A processor has a four-way set associative L1 data cache of 8 KByte in size, with 64-byte cache blocks. The physical addressis 32 bits and data addresses are to the byte. How many bits will be for the tag field?
(A) 18
(B) 19
(C)20
(D) 21
(E) 22
參考答案
答案：[無官方正解]
難度：計算中-1
書單：沒有書單，新增