問題詳情
3.A standard pipelined CPU contains five pipeline stages: instruction fetch (IF), instruction decode (ID),ALU execution (EX), memory access (MA), and result write-back (WB). Assume that the critical pathdelays of the five types of instruction operations IF, ID, EX, MA, WB are 20ms, 20ns, 50ns, 40ns, 30nsrespectively.
【題組】3.1 What is the maximun m working frequency of the above CPU?
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