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• (b) Explain what "Botnet" and "Malware" means.
• (c) Please explain what is "Digital Envelope" and how it works.
• (d) Explain the main techniques used to construct "Bitcoin" and its main network, and what
• 1. 全民國防是結合平時與戰時的國防，戰時則實施　(A)全民精神動員　(B)集體精神動員　(C)全民防衛動員　(D)全國人民動員 快速動員後備、民力、物力和精神力，以發揮全民力量，爭取防衛作戰勝利。
• 【題組】1.6 What is the representable range of the single-precision floating-point numbers?
• 【題組】1.7 Is the distance between two neighboring singlo-precision foating-point numbers the same?
• 【題組】1.8 For a 32-bit two's complement signed fixed-point rep presentation with 16 integer bits
• 【題組】1.9 Continued with the previous 32-bit signed fixed-point representation, what is the representa
• 【題組】1.10 In general, addition of two 32-bit fixed-point numbers can be finished in one clock cycle.H
• 2. 2.1 A processor is busy with computation 40% of aputation 40% of the execution time, and is waiti
• 2.2 If you want to achieve a speedup of 80 for a computation task using 100 processots runningconcur
• 2.3 For an application program running on a multi-processor system with 32 processors, it takes200 n
• 2.4 Assume that 25% operations of a computation task are floating-point operations and averageCPI (c
• 3.A standard pipelined CPU contains five pipeline stages: instruction fetch (IF), instruction decode
• 【題組】3.2 Assume that a computation task contains only 100 instructions and there is no hazard for the
• 【題組】3.3 If we want to reduc ce the pi pipelined stages from 5 to 4 by merging some of the five types
• 【題組】3.4 What is data hazard? Give an assembly language example to show one type of data hazard.
• 【題組】3.5 What is super-pipeline? What are the advantages and disadvantages of super-pipeline design?
• 4.Cache 4.1 How nuny bits in toteal (including the tag bits and vaid bite) are reqvired for dlue tt
• 【題組】4.3 Repeat the above problem for a fully associative cache.
• 【題組】4.4 Compare the advantages and disadvantages of the above three different cache designs. Whichon
• 【題組】4.5 The average mem mory access time (AMAT) per instruction can be expressed asAMAT = time for a
• 【題組】4.6 Assume the miss rate of an instruction cache is 2% and the miss rate of the data cache is 4%
• 【題組】4.7 Suppose that in 1000 memory references, there are 40 misses in the first-level cache and 20m
• 【題組】4.8 Continued with the previous problem, and assuming that there is 1.5 memory references perins